The present invention relates to an information processing apparatus, such as a portable computer, capable of controlling the power consumption by varying the system clock frequency or the like.
In recent years, with the emergence of multifunctional operating systems typified by Microsoft Windows or high-performance CPUs (Central Processing Units) typified by the Intel Pentium Processor, the field of personal computers has also attained a major improvement in their processing functions. Meanwhile, because the power consumption of the computer system tends to increase, efforts have been being made for reduction in power consumption by means of improvement in the IC process or the like. Under the demand for further functional improvement, these means for reducing the power consumption act as effective means, contributing to the reduction in power consumption per unit function, but, in many cases, not attaining a reduction in total value of the power that the CPU consumes. Also, because the time at which the CPU equipped with low power consumption measures is released into the market is delayed from that of non-low power consumption CPUs, portable information equipment (e.g., notebook personal computers), which is generally adopted to use battery drive and whose power consumption need to be low, is forced to use one- or two-previous generation CPUs of low power consumption versions, tending to result in insufficient functions as a system. Under these circumstances, there have been proposed some methods of reducing the power consumption of computer systems.
One known method for reducing the power consumption of computer systems is to lower the CPU clock frequency. As has conventionally been adopted in many laptop or notebook computers, this method is designed to enable the user to select a CPU clock frequency through exclusive key input or the like in the initial state or on the way of use, where selecting a low CPU clock frequency allows the ability of the whole computer system to lower, to thereby attain a reduction in the power consumption. More specifically, for example, operating a 90 MHz clock capable CPU at a 50 MHz clock reduces the power consumption by about one half.
Also, as a conventional power consumption saving function of computer systems, there has been proposed a method of reducing the power consumption of a CPU by detecting occurrence of an event (occurrence of a key input) such as execution of a key sense routine, that the user has performed directly on the computer system, and by shifting the CPU clock frequency to a certain low state, for example, as disclosed in Japanese Patent Laid-Open Publication HEI 7-219670 which is incorporated herein by reference.
The method as described in Japanese Patent Laid-Open Publication HEI 7-219670 is purposed to provide a function of reducing the power consumption of the system without impairing its user friendliness by lowering the system ability during the execution of a key sense routine that involves no high CPU power.
Out of the two conventional methods for reducing the power consumption of computer systems, the former one is intended to restrict the CPU power and reduce the power consumption by lowering the CPU clock frequency. However, restricting the CPU power itself would cause the ability of the computer system to be lowered as well, which can be regarded as essentially equivalent to using one- or two-generation previous CPUs of low power consumption. Furthermore, the method disables the maximum specification abilities inherent in the CPU, which would cause the user discomfort.
The latter method, on the other hand, is intended to reduce the power consumption by lowering the CPU clock frequency only during the execution of the key sense routine that involves no particularly high CPU power, thus having a function of preventing the user from feeling discomfort. However, during the time other than the execution of the key sense routine, this power consumption reduction function will not work. Even during a time period in which no high CPU power is involved, other than the execution of the key sense routine, for example, a time period in which the user thinks about input sentences while using word processor software, the CPU power will not lower, so that wasteful power is consumed in such time periods.
Further, when the value of the CPU clock frequency to be lowered during the execution of the key sense routine is set to a relatively high frequency with a preference for the prevention of user's discomfort, the power consumption reduction effect would lower. Conversely, when the value is set to a relatively low frequency with a preference for the power consumption reduction effect, there is a possibility of causing the user discomfort. Due to the fact that the speed or frequency of key input differs depending on the user and the working contents involved, it is difficult to uniformly set the value of CPU clock frequency to be lowered.